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| FAN5026 Dual DDR/Dual-Output PWM Controller October 2005 FAN5026 Dual DDR/Dual-Output PWM Controller Features Highly flexible dual synchronous switching PWM General Description The FAN5026 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range from 0.9V to 5.5V that are required to power I/O, chip-sets, and memory banks in high-performance computers, set top boxes, and VGA cards. Synchronous rectification contributes to high efficiency over a wide range of loads. Efficiency is even further enhanced by using MOSFET's RDS(ON) as a current sense component. Feed-forward ramp modulation, average current mode control scheme, and internal feedback compensation provide fast response to load transients. Out-of-phase operation with 180 phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR mode of operation one of the channels tracks the output voltage of another channel and provides output current sink and source capability -- features essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5026 monitors these outputs and generates separate PGx (power good) signals when the soft-start is completed and the output is within 10% of its set point. A built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over-voltage conditions go away. Under-voltage protection latches the chip off when either output drops below 75% of its set value after the soft-start sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. If precision current-sensing is required, an external current-sense resistor may optionally be used. controller includes modes for: - DDR mode with in-phase operation for reduced channel interference - 90 phase shifted two-stage DDR Mode for reduced input ripple - Dual Independent regulators 180 phase shifted Complete DDR Memory power solution - VTT Tracks VDDQ/2 - VDDQ/2 Buffered Reference Output Lossless current sensing on low-side MOSFET or Precision current sensing using sense resistor VCC Under-voltage Lockout Wide power input range: 3 to 16V Excellent dynamic response with Voltage Feed-Forward and Average Current Mode control Power-Good Signal Supports DDR-II and HSTL TSSOP28 package Applications DDR VDDQ and VTT voltage generation Desktop computer Graphics cards Ordering Information Part Number FAN5026MTC Temperature Range -40C to 85C Package TSSOP-28 Packing Rails FAN5026MTCX -40C to 85C TSSOP-28 Tape and Reel (c)2005 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Block Diagrams +5 VCC FAN5026 VIN (BATTERY) = 3 to 16V Q1 ILIM1 L OUT1 VOUT1 = 2.5V COUT1 PWM 1 Q2 DDR Q3 ILIM2/ REF2 VIN (BATTERY) L OUT2 VOUT2 = 1.8V COUT2 PWM 2 Q4 Figure 1. Dual Output Regulator +5 VCC FAN5026 Q1 VIN (BATTERY) = 3 to 16V ILIM1 L OUT1 VDDQ = 2.5V COUT1 R PWM 1 Q2 +5 DDR Q3 R VTT = VDDQ/2 COUT2 PG2/REF 1.25V L OUT2 Q4 PWM 2 ILIM2/REF2 Figure 2. Typical Application 2 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Pin Configurations AGND LDRV1 PGND1 SW1 HDRV1 BOOT1 ISNS1 EN1 GND VSEN1 ILIM1 SS1 DDR VIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FAN5026 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC LDRV2 PGND2 SW2 HDRV2 BOOT2 ISNS2 EN2 GND VSEN2 ILIM2/REF2 SS2 PG2/REF2OUT PG1 TSSOP-28 JA = 50C/W; JC = 16C/W. See note below. Note: JA and JC values are determined using a 4 layer, 1" square PCB with 1 ounce copper. Pin Definitions Pin Number 1 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 17 Pin Name AGND LDRV1 LDRV2 PGND1 PGND2 SW1 SW2 HDRV1 BOOT1 BOOT2 ISNS1 ISNS2 EN1 EN2 GND VSEN1 VSEN2 ILIM1 SS1 SS2 Pin Function Description Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET. Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 3. Current Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. Enable. Enables operation when pulled to logic high. Toggling EN will also reset the regulator after a latched fault condition. These are CMOS inputs whose state is indeterminate if left open. Ground. These pins should be tied to AGND for proper operation. Output Voltage Sense. The feedback from the outputs. Used for regulation as well as PG, under-voltage and over-voltage protection and monitoring. Current Limit 1. A resistor from this pin to GND sets the current limit. Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5A current source. 3 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Pin Definitions (Continued) Pin Number 13 14 Pin Name DDR VIN Pin Function Description DDR Mode Control. High = DDR mode. Low = 2 separate regulators operating 180 out of phase. Input Voltage. Normally connected to battery, provides voltage feed-forward to set the amplitude of the internal oscillator ramp. When using the IC for 2-step conversion from 5V input, connect through 100K to ground, which will set the appropriate ramp gain and synchronize the channels 90 out of phase. Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a 10% range of the 0.9V reference. Power Good 2. When not in DDR Mode: Open-drain output that pulls LOW when the VOUT is out of regulation or in a fault condition Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the VDDQ/2 reference. Current Limit 2. When not in DDR Mode, A resistor from this pin to GND sets the current limit. Reference for reg #2 when in DDR Mode. Typically set to VOUT1/2. VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). 15 16 PG1 PG2 / REF2OUT 18 ILIM2 / REF2 VCC 28 Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Parameter VCC Supply Voltage VIN BOOT, SW, ISNS, HDRV BOOT to SW All Other Pins Junction Temperature (TJ) Storage Temperature Lead Soldering Temperature, 10 seconds -0.3 -40 -65 Min. Typ. Max. 6.5 18 24 6.5 VCC+0.3 150 150 300 Units V V V V V C C C Recommended Operating Conditions Parameter Supply Voltage VCC Supply Voltage VIN Ambient Temperature (TA) note 1 -40 Conditions Min. 4.75 Typ. 5 Max. 5.25 16 85 Units V V C 4 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Electrical Specifications Parameter Power Supplies VCC Current Recommended operating conditions, unless otherwise noted. Conditions LDRV, HDRV Open, VSEN forced above regulation point Shut-down (EN=0) VIN = 15V VIN = 0V Rising VCC Falling Min. Typ. 2.2 Max. 3.0 30 Units mA A A A A V V mV VIN Current - Sinking VIN Current - Sourcing VIN Current - Shut-down UVLO Threshold UVLO Hysteresis Oscillator Frequency Ramp Amplitude, pk-pk Ramp Amplitude, pk-pk Ramp Offset Ramp / VIN Gain Ramp / VIN Gain Reference and Soft Start Internal Reference Voltage Soft Start Current (ISS) Soft Start Complete Threshold PWM Converters Load Regulation VSEN Bias Current Under-Voltage Shutdown Over-Voltage Threshold ISNS Over-Current Threshold Minimum Duty Cycle Output Drivers HDRV Output Resistance LDRV Output Resistance 10 -15 4.3 4.1 4.55 4.25 300 255 300 2 1.25 0.5 125 250 0.891 0.9 -5 1.5 30 -30 1 4.75 4.45 345 KHz V V V mV/V mV/V VIN = 16V VIN = 5V VIN 3V 1V < VIN < 3V 0.909 V A V at start-up IOUTX from 0 to 5A, VIN from 5 to 15V as % of set point. 2S noise filter as % of set point. 2S noise filter RILIM= 68.5K see Figure 10. -2 50 70 115 112 10 80 75 120 140 +2 120 80 125 168 % nA % % A % Sourcing Sinking Sourcing Sinking 12 2.4 12 1.2 -86 108 15 4 15 2 -94 116 0.5 1 % % V A % VREF2 V PG (Power Good Output) and Control pins Lower Threshold Upper Threshold PG Output Low Leakage Current PG2/REF2OUT Voltage DDR, EN Inputs Input High Input Low 2 0.8 V as % of set point, 2S noise filter as % of set point, 2S noise filter IPG = 4mA VPULLUP = 5V DDR = 1, 0 mA < IREF2OUT < 10mA 99 1.01 5 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller 5V VDD EN BOOT CBOOT VIN Q1 DDR HDRV SW VOUT Q2 VDD LDRV PGND Q SR PWM RAMP ILIM det. VSEN EA ? SS PGOOD REF2 ISNS ILIM R ILIM VREF PWM S/H L OUT COUT POR/UVLO OVP DDR ADAPTIVE GATE CONTROL LOGIC OSC RAMP CLK VIN RSENSE CURRENT PROCESSING IOUT Reference and Soft Start DDR Figure 3. IC Block Diagram 6 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Typical Applications VIN = 3 to 16V VCC VIN 14 28 6 BOOT1 C1 D1 +5 C9 +5 C4 R3 5 ILIM1 EN1 11 8 12 4 Q1A HDRV1 SW1 C5 L1 VDDQ = 2.5V PWM 1 2 3 Q1B LDRV1 C6 R7 +5 R4 SS1 C2 PGND2 ISNS1 VSEN1 R5 PG1 DDR EN2 SS2 7 15 10 13 23 21 17 24 25 +5 R1 BOOT2 R6 D2 +5 Q2A HDRV2 SW2 C3 C7 L2 VTT = VDDQ/2 1.25V@10mA PG2/REF 16 Q2B R2 C8 PWM 2 27 26 22 19 18 LDRV2 PGND2 ISNS2 VSEN2 ILIM2/REF2 9 20 AGND 1 R8 Figure 4. DDR Regulator Application Table 1. DDR Regulator BOM Description Capacitor 68F, Tantalum, 25V, ESR 150m Capacitor 10nF, Ceramic Capacitor 68F, Tantalum, 6V, ESR 1.8 Capacitor 150nF, Ceramic Capacitor 180F, Specialty Polymer 4V, ESR 15m Capacitor 1000F, Specialty Polymer 4V, ESR 10m Capacitor 0.1F, Ceramic 1.82K, 1% Resistor 56.2K, 1% Resistor 10K, 5% Resistor 3.24K, 1% Resistor 1.5K, 1% Resistor Schottky Diode 30V Inductor 6.4H, 6A, 8.64m Inductor 0.8H, 6A, 2.24m Dual MOSFET with Schottky DDR Controller Qty 1 2 1 2 2 1 1 3 1 1 1 2 2 1 1 2 1 C1 Ref. C2, C3 C4 C5, C7 C6A, C6B C8 C9 R1, R2, R6 R3 R4 R5 R7, R8 D1, D2 L1 L2 Q1, Q2 U1 Vendor AVX Any AVX Any Panasonic Kemet Any Any Any Any Any Any Fairchild Panasonic Panasonic Fairchild Fairchild Part Number TPSV686*025#0150 TAJB686*006 EEFUE0G181R T510E108(1)004AS4115 BAT54 ETQ-P6F6R4HFA ETQ-P6F0R8LFA FDS6986S (note 1) FAN5026 Notes: 1. Suitable for applications of 4A continuous, 6A peak for VDDQ. If continuous operation above 6A is required use single SO-8 packages for Q1A (FDS6612A) and Q1B (FDS6690S) respectively. Using FDS6690S, change R7 to 1200 . Refer to Power MOSFET Selection, page 14 for more information. 2. C6 = 2 X 180F in parallel. 7 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Typical Applications (Continued) VIN = 3 to 16V VCC VIN 14 28 6 BOOT1 C1 D1 C9 +5 C5 L1 2.5V@4A C6 +5 C4 R2 Q1A 5 ILIM1 EN1 SS1 11 8 12 4 HDRV1 SW1 PWM 1 2 3 Q1B LDRV1 PGND2 ISNS1 VSEN1 C2 +5 R3 PG1 R6 R4 7 15 10 R5 VIN EN2 PG2 SS2 21 16 24 17 25 AGND DDR GND GND 1 13 20 9 23 BOOT2 Q2A HDRV2 SW2 D2 +5 C7 L2 1.8V@2A C8 R7 C3 Q2B PWM 2 27 26 22 19 18 LDRV2 PGND2 ISNS2 VSEN2 ILIM2 R8 R9 R1 Figure 5. Dual Regulator Application Table 2. Dual Regulator BOM Description Capacitor 68F, Tantalum, 25V, ESR 95m Capacitor 10nF, Ceramic Capacitor 68F, Tantalum, 6V, ESR 1.8 Capacitor 150nF, Ceramic Capacitor 330F, Poscap, 4V, ESR 40m Capacitor 0.1F, Ceramic 56.2K, 1% Resistor 10K, 5% Resistor 3.24K, 1% Resistor 1.82K, 1% Resistor 1.5K, 1% Resistor Schottky Diode 30V Inductor 6.4H, 6A, 8.64m Dual MOSFET with Schottky DDR Controller Qty 1 2 1 2 2 2 1 1 1 3 2 2 2 1 1 C1 Ref. C2, C3 C4 C5, C7 C6, C8 C9 R1, R2 R3 R4 R5, R8, R9 R6, R7 D1, D2 L1, L2 Q1 U1 Vendor AVX Any AVX Any Sanyo Any Any Any Any Any Any Fairchild Panasonic Fairchild Fairchild Part Number TPSV686*025#095 TAJB686*006 4TPB330ML BAT54 ETQ-P6F6R4HFA FDS6986S (note 1) FAN5026 Note: 1. If currents above 4A continuous required, use single SO-8 packages for Q1A/Q2A (FDS6612A) and Q1B/Q2B (FDS6690S) respectively. Using FDS6690S, change R6/R7 as required. Refer to Power MOSFET Selection, page 14 for more information. 8 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Circuit Description Overview The FAN5026 is a multi-mode, dual channel PWM controller intended for graphic chipset, SDRAM, DDR DRAM or other low output voltage power applications in PC's, VGA Cards and set top boxes. The IC integrates a control circuitry for two synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistor divider. The two synchronous buck converters can operate from either an unregulated DC source (such as a notebook battery) with voltage ranging from 5.0V to 16V, or from a regulated system rail of 3.3V to 5V. In either mode of operation the IC is biased from a +5V source. The PWM modulators use an average current mode control with input voltage feed-forward for simplified feedback loop compensation and improved line regulation. Both PWM controllers have integrated feedback loop compensation that dramatically reduces the number of external components. The FAN5026 can be configured to operate as a complete DDR solution. When the DDR pin is set high, the second channel can provide the capability to track the output voltage of the first channel. The PWM2 converter is prevented from going into hysteretic mode if the DDR pin is set high. In DDR mode, a buffered reference voltage (buffered voltage of the REF2 pin), required by DDR memory chips, is provided by the PG2 pin. CLK VDDQ VTT Figure 6. Noise-Susceptible 180 Phasing for DDR1 In-phase operation is optimal to reduce inter-converter interference when VIN is higher than 5V, (when VIN is from a battery), as can be seen in Figure 7. Since the duty cycle of PWM1 (generating VDDQ) is short, its switching point occurs far away from the decision point for the VTT regulator, whose duty cycle is nominally 50%. CLK VDDQ VTT Figure 7. Optimal In-Phase Operation for DDR1 When VIN 5V, 180 phase shifted operation can be rejected for the same reasons demonstrated Figure 6. In-phase operation with VIN 5V is even worse, since the switch point of either converter occurs near the switch point of the other converter as seen in Figure 8. In this case, as VIN is a little higher than 5V it will tend to cause early termination of the VTT pulse width. Conversely, VTT's switch point can cause early termination of the VDDQ pulse width when VIN is slightly lower than 5V. CLK Converter Modes and Synchronization Table 3. Converter Modes and Synchronization Mode VIN DDR1 DDR2 DUAL +5V ANY VIN Pin R to GND VIN DDR Pin HIGH HIGH LOW PWM 2 w.r.t. PWM1 IN PHASE + 90 + 180 Battery VIN When used as a dual converter (as in Figure 5), out-ofphase operation with 180 degree phase shift reduces input current ripple. For the "2-step" conversion (where the VTT is converted from VDDQ as in Figure 4) used in DDR mode, the duty cycle of the second converter is nominally 50% and the optimal phasing depends on VIN. The objective is to keep noise generated from the switching transition in one converter from influencing the "decision" to switch in the other converter. When VIN is from the battery, it's typically higher than 7.5V. As shown in Figure 6, 180 operation is undesirable since the turn-on of the VDDQ converter occurs very near the decision point of the VTT converter. VDDQ VTT Figure 8. Noise-Susceptible In-Phase Operation for DDR2 These problems are nicely solved by delaying the 2nd converter's clock by 90 as shown in Figure 9. In this way, all switching transitions in one converter take place far away from the decision points of the other converter. 9 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller CLK Current Processing Section The following discussion refers to Figure 10. The current through RSENSE resistor (ISNS) is sampled shortly after Q2 is turned on. That current is held, and summed with the output of the error amplifier. This effectively creates a current mode control loop. The resistor connected to ISNSx pin (RSENSE) sets the gain in the current feedback loop. For stable operation, the voltage induced by the current feedback at the PWM comparator input should be set to 30% of the ramp amplitude at maximum load current and line voltage. The following expression estimates the recommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET's RDS(ON): I LOAD ( MAX ) * R DS ( ON ) * 4.1K R SENSE = ---------------------------------------------------------------------------- - 100 30% * 0.125 * V IN ( MAX ) RSENSE must, however, be kept higher than: I LOAD ( MAX ) * R DS ( ON ) R SENSE ( MIN ) = ---------------------------------------------------------- - 100 150A (2b) (2a) VDDQ VTT Figure 9. Optimal 90 Phasing for DDR2 Initialization and Soft Start Assuming EN is high, FAN5026 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal Power-On Reset function disables the chip. The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin which is charged with a 5A current source. Once CSS has charged to VREF (0.9V) the output voltage will be in regulation. The time it takes SS to reach 0.9V is: 0.9 x C SS T 0.9 = ------------------------5 where T0.9 is in seconds if CSS is in F. When SS reaches 1.5V, the Power Good outputs are enabled and hysteretic mode is allowed. The converter is forced into PWM mode during soft start. (1) 0.17pF 1.5M 300K VSEN 4.14K I1A = ISNS V to I in + I1B = ISNS 9 LDRV in - PGND SS ISNS RSENSE 17pF S/H TO PWM COMP CSS Reference and Soft Start 2.5V 0.9V 4 * ILIM 3 ILIM mirror ILIM RILIM ILIM det. I2 = Figure 10. Current Limit / Summing Circuits 10 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Setting the Current Limit A ratio of ISNS is also compared to the current established when a 0.9 V internal reference drives the ILIM pin. The threshold is determined at the point when the ISNS ILIM x 4 . Since -------------- > --------------------9 3 I LOAD x R DS ( ON ) ISNS = -------------------------------------------100 + R SENSE therefore, Gate Driver Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gateto-source voltage of the lower MOSFET has decreased to less than approximately 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circuit and shoot-through may occur. 0.9V 4 9 x ( 100 + R SENSE ) -I LIMIT = ------------- x -- x --------------------------------------------------R DS ( ON ) R ILIM 3 or 10.8 ( 100 + R SENSE ) R ILIM = -------------- x -----------------------------------------R DS ( ON ) I LIMIT (3a) (3b) Since the tolerance on the current limit is largely dependent on the ratio of the external resistors, it is fairly accurate if the voltage drop on the Switching Node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4%/C (consult the MOSFET datasheet for actual values), so the actual current limit set point will decrease proportional to increasing MOSFET die temperature. A factor of 1.6 in the current limit setpoint should compensate for all MOSFET RDS(ON) variations, assuming the MOSFET's heat sinking will keep its operating die temperature below 125C. Frequency Loop Compensation Due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency determined by load 1 F PO = ----------------------2R O C O (5) Q2 LDRV ISNS RSENSE PGND where RO is load resistance and CO is load capacitance. For this type of modulator, Type 2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an internally compensated error amplifier. Figure 12 shows a Type 2 amplifier and its response along with the responses of a current mode modulator and of the converter. The Type 2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. 1 F Z = --------------------- = 6kHz 2R 2 C 1 1 F P = --------------------- = 600kHz 2R 2 C 2 (6a) Figure 11. Improving Current Sensing Accuracy More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET as shown in Figure 11. This approach causes higher losses, but yields greater accuracy in both VDROOP and ILIMIT. R1 is a low value (e.g. 10m) resistor. Current limit (ILIMIT) should be set sufficiently high as to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.3 is sufficient. In addition, since ILIMIT is a peak current cut-off value, we will need to multiply ILOAD(MAX) by the inductor ripple current (we'll use 25%). For example, in Figure 5 the target for ILIMIT would be: ILIMIT > 1.2 x 1.25 x 1.6 x 6A 14A (4) 11 R1 (6b) This region is also associated with phase `bump' or reduced phase shift. The amount of phase shift reduction depends the width of the region of flat gain and has a maximum value of 90 degrees. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feedforward of VIN to the oscillator ramp. www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller C2 R2 C1 R1 VIN REF EA Out The optimal value of C(Z) is: L ( OUT ) x C ( OUT ) C ( Z ) = -----------------------------------------------------R5 (7) Protection The converter output is monitored and protected against extreme overload, short circuit, over-voltage and undervoltage conditions. C on err or a mp 18 14 0 modulator A sustained overload on an output sets the PGx pin low and latches-off the whole chip. Operation can be restored by cycling the VCC voltage or by toggling the EN pin. If VOUT drops below the under-voltage threshold, the chip shuts down immediately. ve rte r F P0 FZ FP Over-Current Sensing If the circuit's current limit signal ("ILIM det" as shown in Figure 10) is high at the beginning of a clock cycle, a pulse-skipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next 8 clock cycles. If at any time from the 9th to the 16th clock cycle, the "ILIM det" is again reached, the overcurrent protection latch is set, disabling the chip. If "ILIM det" does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. Figure 12. Compensation The zero frequency, the amplifier high frequency gain and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase `boost'. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz...50kHz range gives some additional phase `boost'. Fortunately, there is an opposite trend in mobile applications to keep the output capacitor as small as possible. If a larger inductor value or low ESR values are called for by the application, additional phase margin can be achieved by putting a zero at the LC crossover frequency. This can be achieved with a capacitor across the feedback resistor (e.g. R5 from Figure 5) as shown below. L(OUT) R5 VSEN R6 C(Z) VOUT C(OUT) PGOOD 1 IL SHUTDOWN 2 VOUT 8 CLK 3 CH1 5.0V CH3 2.0A CH2 100mV M 10.0s Figure 14. Over-Current Protection Waveforms Over-Voltage / Under-Voltage Protection Should the VSNS voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure, or for other reasons, the overvoltage protection comparator will force LDRV high. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, will eventually blow the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a `soft' crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated -- a common problem for latched OVP schemes. Figure 13. Improving Phase Margin 12 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point. Should this condition occur, the regulator will shut down. where I is the inductor ripple current and VOUT is the maximum ripple allowed. V IN - V OUT V OUT L = ----------------------------- x -------------F SW x I V IN for this example we'll use: VIN = 12V, VOUT = 2.5V I = 25% x 6A = 1.5A FSW = 300KHz. therefore L 4.4H (10) Over-Temperature Protection The chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of about 150C is reached. Normal operation is restored at die temperature below 125C with internal Power On Reset asserted, resulting in a full soft-start cycle. Design and Component Selection Guidelines As an initial step, define operating input voltage range, output voltage, minimum and maximum load currents for the controller. Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, Inductor ripple current (I) and the allowable ripple voltage (V). V ESR < ------I (11) Setting the Output Voltage The internal reference is 0.9V. The output is divided down by a voltage divider to the VSEN pin (for example, R5 and R6 in Figure 4). The output voltage therefore is: V OUT - 0.9V 0.9V ----------- = -------------------------------R6 R5 (8a) To minimize noise pickup on this node, keep the resistor to GND (R6) below 2K. We selected R6 at 1.82K. Then choose R5: ( 1.82K ) x ( V OUT - 0.9 ) R5 = ------------------------------------------------------------ = 3.24K 0.9 (8b) In addition, the capacitor's ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 5 is 120mV P-P. Some additional ripple will appear due to the capacitance value itself: I V = -----------------------------------------C OUT x 8 x F SW (12) For DDR applications converting from 3.3V to 2.5V, or other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converter's FPWM to GND. When converter's FPWM is GND, the converter's maximum duty cycle will be greater than 90%. When using as a DDR converter with 3.3V input, set up the converter for In-Phase synchronization by tying the VIN pin to +5V. which is only about 1.5mV for the converter in Figure 5 and can be ignored. The capacitor must also be rated to withstand the RMS current which is approximately 0.3 X (I), or about 400mA for the converter in Figure 5. High frequency decoupling capacitors should be placed as close to the loads as physically possible. Output Inductor Selection The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. At light load, the controller can automatically switch to hysteretic mode of operation to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor. V OUT I = 2 x I MIN = -----------------ESR (9) Input Capacitor Selection The input capacitor should be selected by its ripple current rating. Two-Stage Converter Case In DDR mode (Figure 4), the VTT power input is powered by the VDDQ output, therefore all of the input capacitor ripple current is produced by the VDDQ converter. A conservative estimate of the output current required for the 2.5V regulator is: I VTT I REG1 = I VDDQ + ---------2 13 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller As an example, if average IVDDQ is 3A, and average IVTT is 1A, IVDDQ current will be about 3.5A. If average input voltage is 12V, RMS input ripple current will be: I RMS = I OUT ( MAX ) D - D 2 (13) fore is also representative of gate charge (QG). CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. These losses are given by: where D is the duty cycle of the PWM1 converter: V OUT 2.5 D < -------------- = ------V IN 12 therefore: (14) PUPPER = PSW + PCOND 2.5 2.5 2 I RMS = 3.5 ------- - ------- = 1.42A 12 12 (15) V DS x I L P SW = --------------------- x 2 x t S F SW 2 (17a) Dual Converter 180 Phased In Dual mode (Figure 5), both converters contribute to the capacitor input ripple current. With each converter operating 180 out of phase, the RMS currents add in the following fashion: I RMS = I RMS ( 1 ) + I RMS ( 2 ) or ( I1 ) ( D1 - D1 ) + ( I2 ) ( D2 - D2 ) 2 2 2 2 2 2 V OUT 2 P COND = -------------- x I OUT x R DS ( ON ) V IN where: (17b) (16a) I RMS = (16b) PUPPER is the upper MOSFET's total losses, and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 Figure . The driver's impedance and CISS determine t2 while t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS: which for the dual 3A converters of Figure 5, calculates to: I RMS = 1.51A Power MOSFET Selection Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN5026 converter's output voltage is low with respect to its input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should therefore be selected to minimize conduction losses, thereby selecting a MOSFET with low RDS(ON). In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and it's conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge. CISS VDS C GD C ISS ID QGS Q GD 4.5V VSP VTH High-Side Losses Figure shows a MOSFET's switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis there- V GS t1 t2 QG(SW) t3 t4 t5 Figure 15. Switching Losses and QG 14 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller 5V C GD RD HDRV RGATE G CGS SW VIN J-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC app note AN-1029 for SO-8 MOSFET thermal information). Layout Considerations Switching converters, even during normal operation, produce short pulses of current which could cause substantial ringing and be a source of EMI if layout constrains are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and are noise generators. The low power components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing such as SW, HDRV and LDRV, for example. All surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use High Density Interconnect Systems, or micro-vias on these signals. The use of High Density Interconnect Systems or micro-vias on these signals is not recommended. The use of normal thermal vias is left to the discretion of the designer. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gatesource path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respective pins of the IC. The FAN5026 utilizes advanced packaging technologies with lead pitches of 0.6mm. High performance analog semiconductors utilizing narrow lead spacing may require special considerations in PWB design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices. It is not recommended to use any type of rosin or acid core solder, or the use of flux in either the manufacturing or touch up process as these may contribute to corrosion or enable electromigration and/or eddy currents near the sensitive low current signals. When chemicals such as these are used on or near the PWB, it is suggested that the entire PWB be cleaned and dried completely before applying power. Figure 16. Drive Equivalent Circuit Q G ( SW ) Q G ( SW ) t S = -------------------- ----------------------------------------------------I DRIVER VCC - V SP ---------------------------------------------- R DRIVER + R GATE (18) Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS - QTH where QTH is the gate charge required to get the MOSFET to it's threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should also be taken to include the delivery of the MOSFET's gate power (PGATE) in calculating the power dissipation required for the FAN5026: PGATE = QG x VCC x FSW where QG is the total gate charge to reach VCC. (19) Low-Side Losses Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS 0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and we can select Q2 based on RDS(ON) only. Conduction losses for Q2 are given by: P COND = ( 1 - D ) x I OUT x R DS ( ON ) 2 (20) where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and V OUT D = -------------V IN is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1-D) 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the low-side MOSFET, the J-A, and the maximum allowable ambient temperature rise: T J ( MAX ) - T A ( MAX ) P D ( MAX ) = -----------------------------------------------J - A (21) 15 www.fairchildsemi.com FAN5026 Rev. 1.0.5 FAN5026 Dual DDR/Dual-Output PWM Controller Mechanical Dimensions 28-Pin TSSOP -A- 9.7 0.1 0.51 TYP 28 15 -B- 4.16 4.4 0.1 6.4 3.2 14 PIN # 1 IDENT LAND PATTERN RECOMMENDATION 1.2 MAX 0.1 C ALL LEAD TIPS 0.90 -0.10 +0.15 0.2 BA ALL Lead Tips 1.78 0.65 0.42 See Detail A 0.09-0.20 -C- 0.65 0.19-0.30 0.13 0.10 0.05 AB C 12.00 Top & Botom R0.16 GAGE PLANE DIMENSIONS ARE IN MILLIMETERS 0-8 R0.31 .025 NOTES: 0.61 0.1 1.00 SEATING PLANE A. Conforms to JEDEC registration MO-153, variation AB, Ref. Note 6, dated 7/93. B. Dimensions are in millimeters. C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions. D Dimensions and Tolerances per ANsI Y14.5M, 1982 DETAIL A 16 www.fairchildsemi.com FAN5026 Rev. 1.0.5 7.72 FAN5026 Dual DDR/Dual-Output PWM Controller TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FAST ActiveArrayTM FASTrTM BottomlessTM FPSTM Build it NowTM FRFETTM CoolFETTM GlobalOptoisolatorTM CROSSVOLTTM GTOTM DOMETM HiSeCTM EcoSPARKTM I2CTM E2CMOSTM i-LoTM EnSignaTM ImpliedDisconnectTM FACTTM IntelliMAXTM FACT Quiet SeriesTM Across the board. Around the world.TM The Power Franchise Programmable Active DroopTM DISCLAIMER ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC OPTOPLANARTM PACMANTM POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET UniFETTM VCXTM WireTM FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I16 17 www.fairchildsemi.com FAN5026 Rev. 1.0.5 |
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